\section{background}\label{sec:bkground}

With continuously technology scaling, the interconnect performance degrades due to the increasing fraction of interconnect delay and power consumption. 3D stacking provides a promising solution to tackle the interconnect bottleneck by providing vertical connections and smaller chip footprint. In terms of stacking components, 3D ICs can be categorized into TSV-based and interposer-based designs. 

\subsection{TSV-based 3D ICs}
With the capability of vertical connections, multiple dies can stack in TSV-based 3D design, as shown in Figure~\ref{fig:3dtsv}.

The stacking method between two dies can be either face-to-back or face-to-face. Figure~\ref{fig:3dtsv}(a) shows an example of face-to-back stacking, where TSVs are built in the silicon substrate and carry the signal from top tier to bottom tier. In face-to-face stacking as shown in Figure~\ref{fig:3dtsv}(b), micro-bumps directly connect the top metal layers of two tiers without TSVs going through the substrate. By influencing the overall stacking yield and adding bonding cost, TSV-based 3D designs have great impact on the fabrication cost.

\begin{figure}[h]
\includegraphics[width=0.45\textwidth]{figures/3Dtsv.pdf}
\caption{An example of 3D TSV-based stacking, where TSVs are used for vertical signal connections: (a) is the face-to-back stacking method and (b) is the face-to-back stacking method.}\label{fig:3dtsv}
\vspace{-15pt}
\end{figure}

\subsection{Interposer-based 3D ICs}

Silicon interposer is an important component acting as intermediate carrier and wiring device in most of the 3D designs~\cite{zoschke2011}. Interposer stacking can provide an alternative way of die stacking~\cite{ohsawa2001}, as shown in Figure~\ref{fig:3dinterposer}. Different from TSV-based integration, interposer is a silicon layer with interconnect components built in advance~\cite{rao2009,wieland2010,sunohara2008}, indicating the benefit that the interposer fabrication process is independent from die fabrication without interfering the final yield.

\begin{figure}[b]
\includegraphics[width=0.50\textwidth]{figures/interposer.pdf}
\caption{An example of 3D interposer-based stacking, where interposers are silicon device with pre-built TSVs: (a) is stacking chips on one side of interposer and (b) is stacking chips on both sides of interposer.}\label{fig:3dinterposer}
\vspace{-15pt}
\end{figure}

Two stacking methods can be used in interposer-based 3D design: one side and two sides stacking. The first one is putting dies on only one side of the interposer, as shown in Figure~\ref{fig:3dinterposer}(a). The communication is through the TSVs in interposer and the micro-bumps between interposers. In this stacking method, single interposer layer size is determined by the accumulated die size. The second one is bonding dies on both sides of the interposer, forming two tiers stacking with one interposer, as shown in Figure~\ref{fig:3dinterposer}(b). The TSVs act as interconnects for dies on the same tier and inter-tier communication. In this case, single interposer size is bounded by the maximum tier size.

In our cost-efficient design flow, we only consider the two sides stacking scenario with one interposer layer. This stacking method has higher interposer utilization rate and the interconnect behavior between tiers is similar to TSV-based 3D designs. 